As semiconductors continue to decrease in size, the separation of the vias continues to decrease. As the vias move closer together the chamfering at the top may be positioned too close to adjacent vias. If the tops of the vias are positioned too close together the capacitance may increase. There is also a risk of breaking minimum critical dimension rules for the dielectric isolation between the chamfered line and the associated line at the level below belonging to a separate net. Thus, new devices and methods for decreasing via chamfering to allow the back end of line (BEOL) capacitance to stay as low as possible are needed.